In the production, in particular, of a DMOS wafer, the problem arises that not only the electrical parameters of the integrated circuit but also the gate oxide must be tested for faults. This necessitates an increased voltage, which must be applied to the input (the gate of a DMOS transistor). However, owing to the protective device provided against ESD overvoltages, the input voltage is limited to the predetermined limit value of the protective device.
In order to circumvent this problem, the connection between the protective circuit and the input terminal is initially interrupted in the case of known test methods. After the separation of the chips, the connection is then reestablished during assembly by means of an additional working step. This additional working step causes additional costs. The space requirement for the additional connection on the chip is also relatively large, since corresponding lines having connecting tabs have to be provided, and these require an additional silicon surface area and hence, if appropriate, enlarge the chip.